1. Field of the Invention
The present invention relates to a semiconductor device and more particularly, to a semiconductor device with a so-called Metal-Oxide-Semiconductor (MOS) capacitor, and a fabrication method thereof.
2. Description of the Prior Art
Conventionally, a MOS capacitor has been used as one of the electronic components in a semiconductor device.
It is needless to say that a plurality of active areas are defined on a main surface of a semiconductor substrate and a plurality of MOS capacitors are formed in the plurality of active areas. However, only one of the plurality of active areas and only one of the capacitors are explained in this specification for the sake of simplification of description.
A typical example of the conventional semiconductor devices with MOS capacitors is shown in FIGS. 1A to 1E.
First, as shown in FIG. 1A, a patterned photoresist film 102 with a window 102a is formed on a main surface of a p-type semiconductor substrate 101. The window 102a typically has a square or rectangular plan shape.
Next, using the patterned photoresist film 102 as a mask, phosphorus (P) ions are selectively implanted into the substrate 101 through the window 102a of the film 102 with a dose of approximately 1.times.10.sup.12 to 1.times.10.sup.14 atoms/cm.sup.2. The bottom of the ion-implanted region is indicated by the reference numeral 103 in FIG. 1A.
After the photoresist film 102 is stripped, the substrate 101 is subjected to a heat treatment at a temperature of 1000.degree. C. or higher to diffuse the implanted phosphorus ions within the substrate 101, thereby forming an n-type well 104, as shown in FIG. 1B. The well 104 typically has a square or rectangular plan shape.
Subsequently, a silicon nitride (SiN.sub.x) layer 105 with a thickness of approximately 50 to 1000 nm is grown on the well 104 by a Chemical Vapor Deposition (CVD) process or the like. The layer 105 is then patterned to have a specific plan shape such as a square or rectangle by popular patterning processes, as shown in FIG. 1B.
Using the patterned silicon nitride layer 105 as a mask, the substrate 101 is thermally oxidized to selectively grow a field oxide layer 106 at a location where the silicon nitride layer 105 is removed, as shown in FIG. 1C. Thus, an active area 107 is defined by the field oxide layer 106 on the main surface of the substrate 101. The field oxide layer 106 is located on the periphery of the n-type well 104.
After stripping the patterned silicon nitride layer 105, an insulating layer 108 with a thickness of approximately 1 to 100 nm is formed on the whole, exposed surface of the well 104 or the active area 107. This insulating layer 108 is formed simultaneously with the formation process of a gate insulating layer for MOS Field-Effect Transistors (MOSFETs) (not shown) to be provided on the same substrate 101.
A conductive layer (not shown) with a thickness of approximately 100 to 1000 nm is grown over the whole substrate 101 by a CVD process or the like, and then, is patterned to form an electrode 109 on the insulating layer 108, as shown in FIG. 1C. This conductive layer is formed simultaneously with the formation process of gate electrodes for the MOSFETs to be provided on the same substrate 101.
The insulating layer 108 is partially exposed from the electrode 109, as shown in FIG. 1C.
Subsequently, using the electrode 109 as a mask, phosphorus (P) or arsenic (As) ions are selectively implanted into the well 104 through the gap between the electrode 109 and the field oxide layer 106 with a dose of approximately 1.times.10.sup.14 to 1.times.10.sup.16 atoms/cm.sup.2. The bottom of the implanted region are indicated by the reference numeral 110 in FIG. 1D.
Further, the substrate 101 is subjected to a heat treatment at a temperature of 800.degree. C. or higher to activate the implanted ions within the well 104, thereby forming an n.sup.+ -type diffusion region 111 to surround the electrode 109, as shown in FIG. 1E.
Through the above-described process steps, the conventional semiconductor device with the MOS capacitor is obtained. The MOS capacitor is composed of the n-type well 104, the insulating layer 108, and the electrode 109. The n.sup.+ -type diffusion region 111 serves as a contact region for electrical connection to the n-type well layer 104.
With the above-described conventional MOS capacitor, the n-type well 104 and the electrode 109 serve as a pair of electrodes of the capacitor and the insulating layer 10B serves as a dielectric thereof. The n.sup.+ -type diffusion region 111 serves as a contact region for electrical connection.
The conventional semiconductor device as shown in FIG. 1E has a problem that the capacitance of the MOS capacitor may decrease when the electric potential difference between the n-type well 104 and the electrode 109 satisfies a specific condition.
Specifically, when the electric potential of the electrode 109 is lower than that of the n-type well 104, i.e., a backward voltage is applied across the MOS capacitor, a weak inversion region will be formed on the surface of the well 104. When the electric potential of the electrode 109 is further lowered, the weak inversion region will be a strong inversion region.
The weak or strong inversion region causes a depletion region and a channel region in the surface area of the well 104. As a result, a capacitor is formed by the well 104, the depletion region, and the channel region and at the same time, another capacitor is formed by the channel region, the insulating layer 108, and the electrode 109. These two capacitors are electrically connected in cascade. Therefore, the total capacitance of the MOS capacitor is decreased to approximately (1/2) to (1/5) of the normal capacitance where no weak nor strong inversion region are formed.
Accordingly, considering the above capacitance decrease due to the formation of the weak or strong inversion region, it is necessary that the MOS capacitor is designed to have a larger size than that for the required capacitance. This means that the chip area of the MOS capacitor increases, resulting in lowering of the device integration density.
To solve the above problem about the capacitance decrease, the Japanese Non-Examined Patent Publication No. 2-137256 published in May 1990 disclosed an improved structure of the MOS capacitor.
In the conventional, improved structure of the Japanese Non-Examined Patent Publication No. 2-137256, first and second MOS capacitors having the same structure are provided on a semiconductor substrate. The first and second capacitors are electrically connected to each other to be opposite polarities or directions.
With the improved structure of the Japanese Non-Examined Patent Publication No. 2-137256, however, the first and second capacitors need to be located at a comparatively large lateral distance in order to prevent the latch-up phenomenon. This also results in decrease of the device integration density.